1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor storage device in which memory cells are formed on a silicon-on-insulator (SOI) structure.
2. Description of the Related Art
In structures of memory cell portions of conventional nonvolatile semiconductor storage devices, making finer memory cells has limitations for the following reason. Specifically, when the channel length of memory cells is set to 50 nm or less, the on/off ratio of the channel current decreases due to the short channel effect. Decrease in the on/off ratio of the channel current causes transistors of memory cells to malfunction.
Therefore, recently, methods of forming memory cells on an SOI crystal have been proposed (Jpn. Pat. Appln. KOKAI Pub. No. 5-335234, Jpn. Pat. Appln. KOKAI Pub. No. 6-333822, Jpn. Pat. Appln. KOKAI Pub. No. 9-36024). However, it is difficult to form a silicon layer having a large area and good crystal properties on an insulating film, and there is the problem that variations occur between cells. In particular, in devices on an SOI structure using solid-phase crystallization, a mismatch surface having an uncertain position is generated on an embedded insulating film. Therefore, there is the problem that cell transistors are formed on the mismatch surface, and operation thereof become unstable.
When a single-crystal layer is formed on an SOI region by solid-phase crystallization, monocrystallization is performed from opening portions (seed regions) provided in an embedded insulating film toward the SOI region. The growth surface of solid-phase crystallization in this case varies from position to position as the distance from the seed region becomes longer. Therefore, the position of the crystal grain boundary (crystal mismatch surface) determined by the solid-phase crystallization distance from adjacent opening portions differs according to the position.
As a result, for example, the crystal mismatch surface may be formed in just the intermediate position of the seed regions, or may be formed in a position shifted from the intermediate position of the seed regions. Since a plurality of seed portions, that is, opening portions of the insulating film, are provided in the silicon substrate, occurrence of the crystal mismatch surface is inevitable.
Since the crystal properties deteriorate in crystal mismatch surfaces, it is not preferable to provide LSI circuits directly on crystal mismatch surfaces, in terms of reliability of the thermal oxide film of LSI circuits and control of pn junction by a dopant diffusion layer. Therefore, it is necessary to design LSI circuits to avoid a portion of the crystal mismatch surface. The defective region caused by a crystal mismatch surface is not always positioned in the midpoint between opening portions of the SOI region, but may be shifted from the midpoint by about below 1 μm, due to variations of the solid-phase crystallization speed. Supposing that the length of SOI on which solid-phase crystallization can be performed is about 3 μm from opening portions, intervals between opening portions have to be set to about 5 μm. To make room for a defective region, which may occupy 1 μm, around the center of the area of 5 μm without providing any circuit further reduces the occupying proportion of circuits, and increases the chip manufacturing cost.